Sorting a Dependency Graph in Go

This bug doesn’t exist on x86: Exploiting an ARM-only race condition

Clock Gating

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Hi What's up beautiful people? Hope you're having another wonderful Wednesday. If you know anyone who might enjoy this newsletter as well, feel free to share it with them. Also I tried to start a discussion with the author of the frontend philosophy article featured in yesterday's issue, which you can check out if you want. Am I nitpicking language too much? I don't know, you decide, and chime in if you feel like I missed something or you disagree with me. Here is that issue. ==================================================================== Sorting a Dependency Graph in Go Published: 26 October 2021 Tags: go You know what gets more flak than frontend engineers? "Implement algorithm X" in coding interviews. Well... although most of those questions aren't very good measures of how good a fit the candidate will be (in most cases), algorithms are nonetheless important to software engineering. In this article, Andrew Meredith implements one such algorithm in Go in order to build and sort a dependency graph. Read Full Article ==================================================================== This bug doesn’t exist on x86: Exploiting an ARM-only race condition Published: 26 October 2021 Tags: infosec You wanna buy some hack? No? Well you might want to read Stephen Tong's extensive article on a "real-world, modern binary exploitation" that is only relevant to ARM, and not x86 prcoessors. Why? Because it's interesting. Stephen breaks the lengthy article into three main sections; "walkthrough of the binary, and a peek into the mindset of a vulnerability researcher", "memory ordering, lock-free programming, and how this can lead to sneaky bugs", and "exploiting an object lifetime heap corruption bug. How to get arbitrary read and write and finally, a shell". Read Full Article ==================================================================== Clock Gating Published: 26 October 2021 Tags: fpga As Wikipedia states clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation, by removing the clock signal when the circuit is not in use. Okay, easy enough to understand for hardware, but what about programmable hardware, like a FPGA? In this article, the author attempts to implement a clock gating circuit for a FPGA in order to (hypothetically) reduce simulation times. Ultimately, it failed. Read Full Article Want to discuss the issue?  If you want to discuss or comment on this issue, head on over to this page at A Byte of Coding. Thanks for your Support!  Thanks to sponsors and supporters like Євген Грицай, Scott Munro, zturak, pek, Emil Hannesbo, and Joe Hill this newsletter is provided to you for free. If you'd like to also show your support and buy me a monthly meal, you can donate on the Patreon page. It's not necessary, but it lets me know that I'm doing a good job and that you're finding value in the content. Donate Here

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